@article{wangHitchhikersGuideProgramming, title = {The {{Hitchhiker}}’s {{Guide}} to {{Programming}} and {{Optimizing Cache Coherent Heterogeneous Systems}}}, author = {Wang, Zixuan and Mahar, Suyash and Li, Luyi and Park, Jangseon and Kim, Jinpyo and Michailidis, Theodore and Pan, Yue and Shen, Mingyao and Rosing, Tajana and Tullsen, Dean and Swanson, Steven and Zhao, Jishen}, abstract = {We present a thorough analysis of the use of modern heterogeneous systems interconnected by various cachecoherent links, including CXL, NVLink-C2C, and Infinity Fabric. We studied a wide range of server systems that combined CPUs from different vendors and various types of coherent memory devices, including CXL memory expander, CXL pool, CXL shared memory, GH200 GPU, and AMD MI300a HBM. For this study, we developed a heterogeneous memory benchmark suite, H E I M DA L L, to profile the performance of such heterogeneous systems and present a detailed performance comparison across systems. By leveraging H E I M DA L L, we unveiled the detailed architecture design in these systems, drew observations on optimizing performance for workloads, and pointed out directions for future development of cache coherent heterogeneous systems.}, langid = {english}, file = {/home/shrik3/Zotero/storage/HCDXLSM5/Wang et al. - The Hitchhiker’s Guide to Programming and Optimizing Cache Coherent Heterogeneous Systems.pdf} } @book{3207796, author = {Hennessy, John L. and Patterson, David A.}, title = {Computer Architecture, Sixth Edition: A Quantitative Approach}, year = {2017}, isbn = {0128119055}, publisher = {Morgan Kaufmann Publishers Inc.}, address = {San Francisco, CA, USA}, edition = {6th}, abstract = {Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook is fully revised with the latest developments in processor and system architecture. It now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design. Includes a new chapter on domain-specific architectures, explaining how they are the only path forward for improved performance and energy efficiency given the end of Moores Law and Dennard scaling Features the first publication of several DSAs from industry Features extensive updates to the chapter on warehouse-scale computing, with the first public information on the newest Google WSC Offers updates to other chapters including new material dealing with the use of stacked DRAM; data on the performance of new NVIDIA Pascal GPU vs. new AVX-512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization Includes "Putting It All Together" sections near the end of every chapter, providing real-world technology examples that demonstrate the principles covered in each chapter Includes review appendices in the printed text and additional reference appendices available online Includes updated and improved case studies and exercises} } @book{bryantComputerSystemsProgrammers2016, title = {Computer Systems: A Programmer's Perspective}, shorttitle = {Computer Systems}, author = {Bryant, Randal E. and O'Hallaron, David R.}, date = {2016}, edition = {Third edition}, publisher = {Pearson}, location = {Boston}, isbn = {978-0-13-409266-9}, langid = {english}, pagetotal = {1084}, keywords = {Computer systems,Computers,Telecommunication,User interfaces (Computer systems)}, file = {/home/shrik3/Zotero/storage/ZH8I9VKM/Bryant and O'Hallaron - 2016 - Computer systems a programmer's perspective.pdf} } @inproceedings{oberhauserVSyncPushbuttonVerification2021, title = {{{VSync}}: Push-Button Verification and Optimization for Synchronization Primitives on Weak Memory Models}, shorttitle = {{{VSync}}}, booktitle = {Proceedings of the 26th {{ACM International Conference}} on {{Architectural Support}} for {{Programming Languages}} and {{Operating Systems}}}, author = {Oberhauser, Jonas and Chehab, Rafael Lourenco De Lima and Behrens, Diogo and Fu, Ming and Paolillo, Antonio and Oberhauser, Lilith and Bhat, Koustubha and Wen, Yuzhong and Chen, Haibo and Kim, Jaeho and Vafeiadis, Viktor}, date = {2021-04-19}, pages = {530--545}, publisher = {ACM}, location = {Virtual USA}, doi = {10.1145/3445814.3446748}, url = {https://dl.acm.org/doi/10.1145/3445814.3446748}, urldate = {2026-03-19}, abstract = {Implementing highly efficient and correct synchronization primitives on modern Weak Memory Model (WMM) architectures, such as ARM and RISC-V, is very difficult even for human experts. We introduce VSync, a framework to assist in optimizing and verifying synchronization primitives on WMM architectures. VSync automatically detects missing and overly-constrained barriers, while ensuring essential safety and liveness properties. VSync relies on two novel techniques: 1) Adaptive Linear Relaxation (ALR), which utilizes barrier monotonicity and speculation to quickly find a correct maximally-relaxed barrier combination; and 2) Await Model Checking (AMC), which for the first time makes it possible to check termination of await loops on WMMs.}, eventtitle = {{{ASPLOS}} '21: 26th {{ACM International Conference}} on {{Architectural Support}} for {{Programming Languages}} and {{Operating Systems}}}, isbn = {978-1-4503-8317-2}, langid = {english}, file = {/home/shrik3/Zotero/storage/QNKL4D5F/Oberhauser et al. - 2021 - VSync push-button verification and optimization for synchronization primitives on weak memory model.pdf} } @inproceedings{loughlinStopHammerTime2021, title = {Stop! {{Hammer}} Time: Rethinking Our Approach to Rowhammer Mitigations}, shorttitle = {Stop! {{Hammer}} Time}, booktitle = {Proceedings of the {{Workshop}} on {{Hot Topics}} in {{Operating Systems}}}, author = {Loughlin, Kevin and Saroiu, Stefan and Wolman, Alec and Kasikci, Baris}, date = {2021-06}, pages = {88--95}, publisher = {ACM}, location = {Ann Arbor Michigan}, doi = {10.1145/3458336.3465295}, url = {https://dl.acm.org/doi/10.1145/3458336.3465295}, urldate = {2025-06-03}, abstract = {Rowhammer attacks exploit electromagnetic interference among nearby DRAM cells to flip bits, corrupting data and altering system behavior. Unfortunately, DRAM vendors have opted for a blackbox approach to preventing these bit flips, exposing little information about in-DRAM mitigations. Despite vendor claims that their mitigations prevent Rowhammer, recent work bypasses these defenses to corrupt data. Further work shows that the Rowhammer problem is actually worsening in emerging DRAM and posits that system-level support is needed to produce adaptable and scalable defenses. Accordingly, we argue that the systems community can and must drive a fundamental change in Rowhammer mitigation techniques. In the short term, cloud providers and CPU vendors must work together to supplement limited in-DRAM mitigations—ill-equipped to handle rising susceptibility—with their own mitigations. We propose novel hardware primitives in the CPU’s integrated memory controller that would enable a variety of efficient software defenses, offering flexible safeguards against future attacks. In the long term, we assert that major consumers of DRAM must persuade DRAM vendors to provide precise information on their defenses, limitations, and necessary supplemental solutions.}, eventtitle = {{{HotOS}} '21: {{Workshop}} on {{Hot Topics}} in {{Operating Systems}}}, isbn = {978-1-4503-8438-4}, langid = {english}, file = {/home/shrik3/Zotero/storage/8FASYYY6/Loughlin et al. - 2021 - Stop! Hammer time rethinking our approach to rowhammer mitigations.pdf} } @inproceedings{giontaHideMProtectingContents2015, title = {{{HideM}}: {{Protecting}} the {{Contents}} of {{Userspace Memory}} in the {{Face}} of {{Disclosure Vulnerabilities}}}, shorttitle = {{{HideM}}}, booktitle = {Proceedings of the 5th {{ACM Conference}} on {{Data}} and {{Application Security}} and {{Privacy}}}, author = {Gionta, Jason and Enck, William and Ning, Peng}, date = {2015-03-02}, pages = {325--336}, publisher = {ACM}, location = {San Antonio Texas USA}, doi = {10.1145/2699026.2699107}, url = {https://dl.acm.org/doi/10.1145/2699026.2699107}, urldate = {2023-12-20}, abstract = {Memory disclosure vulnerabilities have become a common component for enabling reliable exploitation of systems by leaking the contents of executable data. Previous research towards protecting executable data from disclosure has failed to gain popularity due to large performance penalties and required architectural changes. Other research has focused on protecting application data but fails to consider a vulnerable application that leaks its own executable data.}, eventtitle = {{{CODASPY}}'15: {{Fifth ACM Conference}} on {{Data}} and {{Application Security}} and {{Privacy}}}, isbn = {978-1-4503-3191-3}, langid = {english}, keywords = {/unread}, file = {/home/shrik3/Zotero/storage/J8ZVDJCL/Gionta et al. - 2015 - HideM Protecting the Contents of Userspace Memory.pdf} } @article{milenkovicDemystifyingIntelBranch, title = {Demystifying {{Intel Branch Predictors}}}, author = {Milenkovic, Milena and Milenkovic, Aleksandar and Kulick, Jeffrey}, abstract = {Improvement of branch predictors has been one of the focal points of computer architecture research during the last decade, ranging from two-level predictors to complex hybrid mechanisms. Most research efforts try to use real, already implemented, branch predictor sizes and organizations for comparison and evaluation.}, langid = {english}, keywords = {/unread}, file = {/home/shrik3/Zotero/storage/BU6M2PPF/Milenkovic et al. - Demystifying Intel Branch Predictors.pdf} } @online{mckenneyParallelProgrammingHard2022, title = {Is {{Parallel Programming Hard}}, {{And}}, {{If So}}, {{What Can You Do About It}}? ({{Release}} V2022.09.25a)}, shorttitle = {Is {{Parallel Programming Hard}}, {{And}}, {{If So}}, {{What Can You Do About It}}?}, author = {McKenney, Paul E.}, date = {2022-09-25}, eprint = {1701.00854}, eprinttype = {arXiv}, eprintclass = {cs}, url = {http://arxiv.org/abs/1701.00854}, urldate = {2023-03-24}, abstract = {The purpose of this book is to help you program shared-memory parallel systems without risking your sanity. Nevertheless, you should think of the information in this book as a foundation on which to build, rather than as a completed cathedral. Your mission, if you choose to accept, is to help make further progress in the exciting field of parallel programming-progress that will in time render this book obsolete. Parallel programming in the 21st century is no longer focused solely on science, research, and grand-challenge projects. And this is all to the good, because it means that parallel programming is becoming an engineering discipline. Therefore, as befits an engineering discipline, this book examines specific parallel-programming tasks and describes how to approach them. In some surprisingly common cases, these tasks can be automated. This book is written in the hope that presenting the engineering discipline underlying successful parallel-programming projects will free a new generation of parallel hackers from the need to slowly and painstakingly reinvent old wheels, enabling them to instead focus their energy and creativity on new frontiers. However, what you get from this book will be determined by what you put into it. It is hoped that simply reading this book will be helpful, and that working the Quick Quizzes will be even more helpful. However, the best results come from applying the techniques taught in this book to real-life problems. As always, practice makes perfect. But no matter how you approach it, we sincerely hope that parallel programming brings you at least as much fun, excitement, and challenge that it has brought to us!}, langid = {english}, pubstate = {prepublished}, keywords = {68-01 68M20 68N19 68N25 68N30,Computer Science - Distributed Parallel and Cluster Computing,D.1.3,D.4.1,D.4.8,E.1,F.1.2}, file = {/home/shrik3/Zotero/storage/HUQIBR6K/McKenney - 2022 - Is Parallel Programming Hard, And, If So, What Can.pdf} } @book{herlihyArtMultiprocessorProgramming2011, title = {The {{Art}} of {{Multiprocessor Programming}}}, author = {Herlihy, Maurice and Shavit, Nir}, date = {2011}, publisher = {Elsevier Science}, location = {Burlington}, abstract = {This book is the first comprehensive presentation of the principles and tools available for programming multiprocessor machines. It is of immediate use to programmers working with the new architectures. For example, the next generation of computer game consoles will all be multiprocessor-based, and the game industry is currently struggling to understand how to address the programming challenges presented by these machines.This change in the industry is so fundamental that it is certain to require a significant response by universities, and courses on multicore programming will become a staple}, isbn = {978-0-12-370591-4}, langid = {english}, pagetotal = {529}, file = {/home/shrik3/Zotero/storage/QF8QBFG5/Herlihy and Shavit - 2011 - The Art of Multiprocessor Programming.pdf} } @article{leeLibmpkSoftwareAbstraction, title = {Libmpk: {{Software Abstraction}} for {{Intel Memory Protection Keys}} ({{Intel MPK}})}, author = {Lee, Soyeon Park Sangho and Moon, Wen Xu Hyungon and Kim, Taesoo}, abstract = {Intel Memory Protection Keys (MPK) is a new hardware primitive to support thread-local permission control on groups of pages without requiring modification of page tables. Unfortunately, its current hardware implementation and software support suffer from security, scalability, and semantic problems: (1) vulnerable to protection-key-use-after-free; (2) providing the limited number of protection keys; and (3) incompatible with mprotect()’s process-based permission model.}, langid = {english}, keywords = {/unread}, file = {/home/shrik3/Zotero/storage/BI2256NP/Lee et al. - libmpk Software Abstraction for Intel Memory Prot.pdf} }